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hd66774 rev. 1.0 july 2002 1 hd66774 240-channel gate driver for color-tft liquid crystal displays rev.1. 0 july 2002 description hd667 74 is a gate-driver ic for system s with color -tft- liquid - crystal dot-matrix graphic displays . it incorporates a circuit for driving 240 channels of tft gate-line driving and all the power-supply circuits that are required for liquid crystal displays, and realizes the liquid crystal display by adding only an external capacitor. when used with the hd66770 396-channel source driver with on-chip ram, and used with the hd66772 528-channel source driver with on-chip ram, this lsi is suitable for color tft displays of cellular phones having 132-by-176 and 176-by-240 dots, respectively. features tft gate-line driving circuits ? 240 outputs gate-line scanning ? centering-screen function (vertically separated, comb type) internal power-supply circuit ? step-up circuit: five to nine times, positive-polarity inversion ? structure of tft-display retention capacitor: cst or cadd alternating functions for tft-display counter-electrode power supply ? n-line alternating drive of vcom (vgoff is also available for n-line alternating drive for cadd) ? adjustment of vcom (vgoff) amplitude: internal 22-level digital potentiometer output power-supply voltage ? for the source driver: ddvdh - gnd = 4.5 to 5.5 v (power supply for hd66770/772 liquid crystal output circuits), vdh - gnd = 3.0 to ddvdh-0.5v (reference power supply for hd66770/772 grayscale voltages)
hd66774 rev. 1.0 july 2002 2 ? for the tft-display counter electrode: vcom amplitude = 6 v (max), vcomh - gnd = 3.0v to vdh , vcoml - gnd = 1.0 v to vcl + 0.5 v. mode setting ? serial transfer from the hd66770/772 source driver low-power consumption ? equalizing function and the switching performance of step-up circuits and operational amplifiers input power-supply voltage ? v cc - gnd = 1.7 to 3. 6 v ? vci - gnd = 2.5 to 3.6 v (internal reference power-supply voltage) pad arrangement ? wiring-through area for high-level mounting type number type number external appearance HCD66774bp die with au bump
hd66774 rev. 1.0 july 2002 3 pin functions table 1 pin functions signal name quantity * input/ output connected to function v cc1, vcc2 2 input power supply gnd 1 input power supply vcc-gnd: a logic-circuit power supply. supply the same voltage as that for hd66770/772. vcc1 and vcc2 are equivalent. supply the voltage to either or both. vdh 1 output capacitor for stabilization, hd66770/772 a reference power supply for the hd66770/772 source-driver grayscale voltage. adjust the vdh level with vreg1out because the vreg1out input voltage is output as the output level. connect a capacitor for stabilization. vgh 1 input vlout2 or power supply a power supply for the gate-line driving circuit, and a positive-side power supply for tft-gate on level, internal step-up circuits, bias circuits, and operational amplifiers. connect vlout2. when vlout2 is not used, connect an external-voltage power supply lower than 16.5 v. vgl 1 input vlout3 or power supply a power supply for the gate-line driving circuit, and a negative-side power supply for the power supply for the gate-line driving circuit, internal step-up circuits, bias circuits, and operational amplifiers. connect vlout3. when vlout3 is not used, connect an external-voltage power supply higher than -16.5 v. vci 1 input vcc or power supply a power supply for the analog circuit. connect a 2.5- to 3.6-v external-voltage power supply. vciout 1 output vci1 and capacitor for stabilization or open outputs the internal reference voltage generated between vci and gnd. the internal reference voltage can be set by a register. vci1 1 input vciout or power supply a step-up voltage for step-up circuit 1. connect vciout or an external power supply lower than 2.75 v. vlout1 1 output ddvdh and capacitor for stabilization or open outputs a voltage that doubles or triples the voltage from step-up voltage vci1. the step-up factor can be set in an internal register. connect a capacitor for stabilization. when this pin is not used, leave it open.
hd66774 rev. 1.0 july 2002 4 table 1 pin functions (cont) signal name quantity * input/ output connected to function ddvdh 1 input vlout1 or power supply and hd66770/772 a power supply for outputting the hd66770/772 source driver liquid crystal. connect this pin to vlout1. when vlout1 is not used, connect an external power supply lower than 5.5 v. vci2 1 input vlout1 or power supply a reference voltage in step-up circuit 2. connect this pin to vlout1. when vlout1 is not used, connect an external power supply lower than 5.5 v. vlout2 1 output vgh, capacitor for stabilization or open a voltage that doubles, triples, or quadruples, and outputs a voltage between ddvdh and gnd in step-up circuit 2. the step-up factor can be set in an internal register. connect a capacitor for stabilization. when this pin is not used, leave it open. vci3 1 input vlout2 or power supply a reference voltage in step-up circuit 3. connect this pin to vlout2. when vlout2 is not used, connect an external power supply lower than 16.5 v. vlout3 1 output vgl, capacitor for stabilization or open a voltage that outputs a voltage between vlout2 and gnd as an equivalent negative voltage in step-up circuit 3. connect a capacitor for stabilization. when this pin is not used, leave it open. vci4 1 input vcc or vci or power supply a reference voltage in step-up circuit 4. connect vci or an external power supply lower than 2.5 v to 3.6 v. vlout4 1 output vcl and capacitor for stabilization or open a voltage that outputs a voltage between vci4 and gnd as an equivalent negative voltage in step-up circuit 4. connect a capacitor for stabilization and the vcl pin. when this pin is not used, leave it open. vcl 1 input vlout4 or power supply a power supply for generating vcoml. when vcoml is a negative voltage, connect vlout4 or an external power supply of ? 3.6 to ? 2.5v.
hd66774 rev. 1.0 july 2002 5 table 1 pin functions (cont) signal name quantity * input/ output connected to function vreg1out 1 output capacitor for stabilization and vreg1 or open this pin generates and outputs a reference voltage for vreg1 between ddvdh and gnd from the reference voltage between vci and gnd that is internally generated. the amplification can be set in an internal register. connect this pin to vreg1 and a capacitor for stabilization. when this pin is not used, leave it open. vreg1 1 input vreg1out or power supply a reference voltage for generating vcom. connect vreg1out. when vreg1out is not used, connect an external power supply lower than ddvdh. vreg2out 1 output capacitor for stabilization and vreg2 or open this pin generates and outputs a reference voltage for vreg2 between gnd and vgl from the reference voltage between vci and gnd that is internally generated. the amplification can be set in an internal register. connect this pin to vreg2 and a capacitor for stabilization. when this pin is not used, leave it open. vreg2 1 input vreg2out or power supply a reference voltage for generating vgoff. connect vreg2out. when vreg2out is not used, connect an external power supply lower than vgl. c11+, c11- to c23 +, c23- 10 - step-up capacitor connect the step-up capacitor according to the step-up factor. when the internal step-up circuit is not used, leave this pin open. c31+, c31- 2 - step-up capacitor connect a step-up capacitor for generating the vgl level from the vgh and gnd levels. when the internal step-up circuit is not used, leave these pins open. c41+, c41- 2 - step-up capacitor connect a step-up capacitor for generating the ? vci4 level from the vci4 and gnd levels. when the internal step-up circuit is not used, leave these pins open. vcom1 vcom2 vcom3 3 output tft-display common electrode a power supply for the tft-display common electrode. when the reversing vcom alternation is not driven, the amplitude between vcomh and vcoml is output. the alternating cycle can be set by the m pin. connect this pin to the tft-display common electrode.
hd66774 rev. 1.0 july 2002 6 table 1 pin functions (cont) signal name quantity * input/ output connected to function vcomr 1 input variable resistor or open a reference voltage of vcomh. when vcomh is externally adjusted, halt the internal adjuster of vcomh by setting the register and insert a variable resistor between vdh and gnd. when this pin is not externally adjusted, leave it open and adjust vcomh by setting the internal register. vcomh 1 output capacitor for stabilization this pin indicates a high level of vcom generated in driving the vcom alternation. connect this pin to the capacitor for stabilization. vcoml 1 output capacitor for stabilization or open this pin indicates a low level of vcom. an internal register can be used to adjust the voltage. connect this pin to a capacitor for stabilization. when the vcomg bit is low, the vcoml output stops and a capacitor for stabilization is not needed. vgoffout 1 output vgoff or open an output power supply for driving the gate line. alternation can be driven by synchronizing vcom with the setting of the internal register. set the internal register according to the structure of the tft-display retention capacitor. for the amplitude at the alternation driving, this pin outputs a voltage between vcomh and vcoml with the vgoffl reference voltage. vgoff 1 input capacitor for stabilization, and vgoffout or power supply this pin is a negative voltage at the tft-gate off level. connect this pin to vgoffout. when vgoffout is not used, connect an external- voltage power supply higher than the vgl voltage. vgoffh 1 output capacitor for stabilization or open when the vgoff alternation is driven, this pin indicates a high level of vgoffout. connect this pin to a capacitor for stabilization. when the cad bit is low, the vgoffh output stops and a capacitor for stabilization is not needed. vgoffl 1 output capacitor for stabilization the vgoffout voltage when the vgoff alternation is not driven. when the vgoff alternation is driven, this pin indicates a low level of vgoffout. an internal register can be used to adjust the voltage. connect this pin to a capacitor for stabilization. regn, regp 2 input/ output open or capacitor for stabilization test pins for vreg1out, vciout, and vreg2out. leave these pins open.
hd66774 rev. 1.0 july 2002 7 table 1 pin functions (cont) signal name quantity * input/ output connected to function m 1 input m of hd66770/772 inputs alternating signal of vcom and vgoff. the following levels are output according to the status of m: low: vcoml or vgoffl , high: vcomh or vgoffh when the vcomg bit is low, the vcoml output stops and the low level of vcom is output as gnd. when the cad bit is low, the vgoffh output stops. eq 1 input gnd or eq of hd66770/772 when the vcom alternation is driven, the output of vcom or vgoffout is hi-z at the transition timing of vcom or vgoffout. the following levels are output according to the status of eq: note: when eq = high, the output status of vgoffout depends on the mode setting of the structure of the tft-display retention capacitor. for the mode setting, refer to the instructions section. when eq is not used, connect this pin to gnd. dcclk 1 input dcclk of hd66770/772 a clock for the step-up circuits supplied from hd66770/772. cl1 1 input cl1 of hd66770/772 clock input pin supplied from hd66770/772. gate line output changes at the falling edge of this signal. this signal is supplied from hd66770/772. flm 1 input flm of hd66770/772 performs frame synchronization with the source driver. this signal is supplied from hd66770/772. disptmg 1 input disptmg of hd66770/772 display-off signal. this signal becomes valid asynchronously with the flm and cl1. high: normal output; low: all output vgoff. gcl 1 input gcl of hd66770/772 operates as a clock for the transfer of register settings. latches data on the rising edge of the clock. gda 1 input gda of hd66770/772 operates as the data for the transfer of register settings. gcs* 1 input gcs* of hd66770/772 a chip-select signal. low: select ed (data - transfer enabled), high: not select ed (data-transfer disabled) reset* 1 input external reset circuit the reset pin. when a low level is input here, the lsi is reinitialized. be sure to apply a signal to this pin during the system ? s power-on reset.
hd66774 rev. 1.0 july 2002 8 table 1 pin functions (cont) signal name quantity * input/ output connected to function scm1, 2 2 input vcc or gnd input for selecting the scan mode. must be fixed to vcc or gnd depending on the selected scan mode. opoff 1 input vcc or gnd when opoff = vcc, the operation of the operational amplifier stops. (at this time, the function is ap2-0 = (0,0,0) or equivalent.) when the voltage for driving the gate circuit is supplied from the external power supply voltage, opoff = vcc should be satisfied. when it is supplied from the internal power supply voltage, opoff = gnd must be satisfied. g1-240 240 output liquid crystal output an output signal to the gate line. outputs vgh as the gate-line selection level, or vgoff as the gate-line non-selection level. gtest1-4 4 output liquid crystal output or open dummy gate outputs. when cad bit is high, output vgh and vgoff level. when cad is low, output vgoff level. when this pin is not used, leave it open. testa1 1 input/ output test pin a test pin for the vcomh output. leave it open or connect a capacitor for stabilization according to the display quality. testa2 1 input/ output test pin a test pin for the vcoml output. leave it open or connect a capacitor for stabilization according to the display quality. testa3 1 input/ output test pin a test pin for the vgoffh output. leave it open or connect a capacitor for stabilization according to the display quality. testa4 1 input/ output test pin a test pin for the vcoml output. leave it open or connect a capacitor for stabilization according to the display quality. pontest dctest2 2 input gnd test pins. connect gnd. vtest 1 input/ output test pin a test pin. must be left open. note: the quantity does not match the number of pads.
hd66774 rev. 1.0 july 2002 9 HCD66774bp pad arrangement
hd66774 rev. 1.0 july 2002 10 HCD66774bp pad coordinates the pad coordinates are shown below. the pad numbers in the pad arrangement correspond to the numbers in the following table that lists the pad center coordinates with the chip-centered origin.
hd66774 rev. 1.0 july 2002 11 no. pin name x (um) y (um) no. pin name x (um) y (um) no. pin name x (um) y (um) 1 dummy1 -6870 -1470 61 vcoml -1260 -1437 121 gcl 3280 -1460 2 vcom1 -6680 -1437 62 testa4 -1160 -1437 122 gcs* 3380 -1460 3 vcom1 -6580 -1437 63 vcomh -1060 -1437 123 gda 3480 -1460 4 dummy5 -6480 -1437 64 testa1 -960 -1437 124 eq 3580 -1460 5 vcom2 -6380 -1437 65 vcomr -860 -1437 125 m 3680 -1460 6 vcom2 -6280 -1437 66 vreg1out -760 -1437 126 flm 3780 -1460 7 c31- -6180 -1437 67 vreg1 -660 -1437 127 cl1 3880 -1460 8 c31+ -6080 -1437 68 regn -560 -1437 128 disptmg 3980 -1460 9 c21- -5980 -1437 69 regp -460 -1437 129 reset* 4080 -1460 10 c21+ -5880 -1437 70 testa2 -360 -1437 130 vccdmy 4180 -1460 11 c22- -5780 -1437 71 vtest -260 -1437 131 scm1 4280 -1460 12 c22+ -5680 -1437 72 vcc1 -160 -1437 132 scm2 4380 -1460 13 c23- -5580 -1437 73 vcc1 -60 -1437 133 gnddmy 4480 -1460 14 c23+ -5480 -1437 74 gnd 40 -1437 134 dctest 4580 -1460 15 c41- -5380 -1437 75 gnd 140 -1437 135 pontest 4680 -1460 16 c41+ -5280 -1437 76 vcc2 240 -1437 136 opoff 4780 -1460 17 c11- -5180 -1437 77 vcc2 340 -1437 137 vcom3 4880 -1437 18 c11+ -5080 -1437 78 vci4 440 -1437 138 vcom3 4980 -1437 19 c12- -4980 -1437 79 vci 540 -1437 139 gtest2 5075 -1460 20 c12+ -4880 -1437 80 vci 640 -1437 140 g2 5135 -1460 21 vgl -4780 -1437 81 idummy17 740 -1460 141 g4 5195 -1460 22 vgl -4680 -1437 82 idummy18 800 -1460 142 g6 5255 -1460 23 vlout3 -4580 -1437 83 idummy19 860 -1460 143 g8 5315 -1460 24 vci3 -4480 -1437 84 idummy20 920 -1460 144 g10 5375 -1460 25 vgh -4380 -1437 85 idummy21 980 -1460 145 g12 5435 -1460 26 vgh -4280 -1437 86 idummy22 1040 -1460 146 g14 5495 -1460 27 vlout2 -4180 -1437 87 idummy23 1100 -1460 147 g16 5555 -1460 28 vcl -4080 -1437 88 idummy24 1160 -1460 148 g18 5615 -1460 29 vcl -3980 -1437 89 idummy25 1220 -1460 149 g20 5675 -1460 30 vlout4 -3880 -1437 90 idummy26 1280 -1460 150 g22 5735 -1460 31 vci1 -3780 -1437 91 idummy27 1340 -1460 151 g24 5795 -1460 32 vciout -3680 -1437 92 idummy28 1400 -1460 152 g26 5855 -1460 33 idummy1 -3520 -1460 93 idummy29 1460 -1460 153 g28 5915 -1460 34 idummy2 -3460 -1460 94 idummy30 1520 -1460 154 g30 5975 -1460 35 idummy3 -3400 -1460 95 idummy31 1580 -1460 155 g32 6035 -1460 36 idummy4 -3340 -1460 96 idummy32 1640 -1460 156 g34 6095 -1460 37 idummy5 -3280 -1460 97 idummy33 1700 -1460 157 g36 6155 -1460 38 idummy6 -3220 -1460 98 idummy34 1760 -1460 158 g38 6215 -1460 39 idummy7 -3160 -1460 99 idummy35 1820 -1460 159 g40 6275 -1460 40 idummy8 -3100 -1460 100 idummy36 1880 -1460 160 g42 6335 -1460 41 idummy9 -3040 -1460 101 idummy37 1940 -1460 161 g44 6395 -1460 42 idummy10 -2980 -1460 102 idummy38 2000 -1460 162 g46 6455 -1460 43 idummy11 -2920 -1460 103 idummy39 2060 -1460 163 g48 6515 -1460 44 idummy12 -2860 -1460 104 idummy40 2120 -1460 164 g50 6575 -1460 45 idummy13 -2800 -1460 105 idummy41 2180 -1460 165 g52 6635 -1460 46 idummy14 -2740 -1460 106 idummy42 2240 -1460 166 g54 6695 -1460 47 idummy15 -2680 -1460 107 idummy43 2300 -1460 167 g56 6755 -1460 48 idummy16 -2620 -1460 108 idummy44 2360 -1460 168 dummy2 6870 -1470 49 vdh -2460 -1437 109 idummy45 2420 -1460 169 g58 6860 -1280 50 vci2 -2360 -1437 110 idummy46 2480 -1460 170 g60 6860 -1220 51 ddvdh -2260 -1437 111 idummy47 2540 -1460 171 g62 6860 -1160 52 ddvdh -2160 -1437 112 idummy48 2600 -1460 172 g64 6860 -1100 53 vlout1 -2060 -1437 113 idummy49 2660 -1460 173 g66 6860 -1040 54 vgoff -1960 -1437 114 idummy50 2720 -1460 174 g68 6860 -980 55 vgoffout -1860 -1437 115 idummy51 2780 -1460 175 g70 6860 -920 56 vgoffh -1760 -1437 116 idummy52 2840 -1460 176 g72 6860 -860 57 vgoffl -1660 -1437 117 idummy53 2900 -1460 177 g74 6860 -800 58 testa3 -1560 -1437 118 idummy54 2960 -1460 178 g76 6860 -740 59 vreg2 -1460 -1437 119 idummy55 3020 -1460 179 g78 6860 -680 60 vreg2out -1360 -1437 120 dcclk 3180 -1460 180 g80 6860 -620
hd66774 rev. 1.0 july 2002 12 no. pin name x (um) y (um) no. pin name x (um) y (um) no. pin name x (um) y (um) 181 g82 6860 -560 241 g200 5000 1460 301 odummy39 1340 1460 182 g84 6860 -500 242 g202 4940 1460 302 odummy40 1280 1460 183 g86 6860 -440 243 g204 4880 1460 303 odummy41 1220 1460 184 g88 6860 -380 244 g206 4820 1460 304 odummy42 1160 1460 185 g90 6860 -320 245 g208 4760 1460 305 odummy43 1100 1460 186 g92 6860 -260 246 g210 4700 1460 306 odummy44 1040 1460 187 g94 6860 -200 247 g212 4640 1460 307 odummy45 980 1460 188 g96 6860 -140 248 g214 4580 1460 308 odummy46 920 1460 189 g98 6860 -80 249 g216 4520 1460 309 odummy47 860 1460 190 g100 6860 -20 250 g218 4460 1460 310 odummy48 800 1460 191 g102 6860 40 251 g220 4400 1460 311 odummy49 740 1460 192 g104 6860 100 252 g222 4340 1460 312 odummy50 680 1460 193 g106 6860 160 253 g224 4280 1460 313 odummy51 620 1460 194 g108 6860 220 254 g226 4220 1460 314 odummy52 560 1460 195 g110 6860 280 255 g228 4160 1460 315 odummy53 500 1460 196 g112 6860 340 256 g230 4100 1460 316 odummy54 440 1460 197 g114 6860 400 257 g232 4040 1460 317 odummy55 380 1460 198 g116 6860 460 258 g234 3980 1460 318 odummy56 320 1460 199 g118 6860 520 259 g236 3920 1460 319 odummy57 260 1460 200 g120 6860 580 260 g238 3860 1460 320 odummy58 200 1460 201 g122 6860 640 261 g240 3800 1460 321 odummy59 140 1460 202 g124 6860 700 262 gtest4 3740 1460 322 odummy60 80 1460 203 g126 6860 760 263 odummy1 3620 1460 323 odummy61 20 1460 204 g128 6860 820 264 odummy2 3560 1460 324 odummy62 -40 1460 205 g130 6860 880 265 odummy3 3500 1460 325 odummy63 -100 1460 206 g132 6860 940 266 odummy4 3440 1460 326 odummy64 -160 1460 207 g134 6860 1000 267 odummy5 3380 1460 327 odummy65 -220 1460 208 g136 6860 1060 268 odummy6 3320 1460 328 odummy66 -280 1460 209 g138 6860 1120 269 odummy7 3260 1460 329 odummy67 -340 1460 210 g140 6860 1180 270 odummy8 3200 1460 330 odummy68 -400 1460 211 g142 6860 1240 271 odummy9 3140 1460 331 odummy69 -460 1460 212 g144 6860 1300 272 odummy10 3080 1460 332 odummy70 -520 1460 213 dummy3 6870 1470 273 odummy11 3020 1460 333 odummy71 -580 1460 214 g146 6620 1460 274 odummy12 2960 1460 334 odummy72 -640 1460 215 g148 6560 1460 275 odummy13 2900 1460 335 odummy73 -700 1460 216 g150 6500 1460 276 odummy14 2840 1460 336 odummy74 -760 1460 217 g152 6440 1460 277 odummy15 2780 1460 337 odummy75 -820 1460 218 g154 6380 1460 278 odummy16 2720 1460 338 odummy76 -880 1460 219 g156 6320 1460 279 odummy17 2660 1460 339 odummy77 -940 1460 220 g158 6260 1460 280 odummy18 2600 1460 340 odummy78 -1000 1460 221 g160 6200 1460 281 odummy19 2540 1460 341 odummy79 -1060 1460 222 g162 6140 1460 282 odummy20 2480 1460 342 odummy80 -1120 1460 223 g164 6080 1460 283 odummy21 2420 1460 343 odummy81 -1180 1460 224 g166 6020 1460 284 odummy22 2360 1460 344 odummy82 -1240 1460 225 g168 5960 1460 285 odummy23 2300 1460 345 odummy83 -1300 1460 226 g170 5900 1460 286 odummy24 2240 1460 346 odummy84 -1360 1460 227 g172 5840 1460 287 odummy25 2180 1460 347 odummy85 -1420 1460 228 g174 5780 1460 288 odummy26 2120 1460 348 odummy86 -1480 1460 229 g176 5720 1460 289 odummy27 2060 1460 349 odummy87 -1540 1460 230 g178 5660 1460 290 odummy28 2000 1460 350 odummy88 -1600 1460 231 g180 5600 1460 291 odummy29 1940 1460 351 odummy89 -1660 1460 232 g182 5540 1460 292 odummy30 1880 1460 352 odummy90 -1720 1460 233 g184 5480 1460 293 odummy31 1820 1460 353 gtest3 -1860 1460 234 g186 5420 1460 294 odummy32 1760 1460 354 g239 -1920 1460 235 g188 5360 1460 295 odummy33 1700 1460 355 g237 -1980 1460 236 g190 5300 1460 296 odummy34 1640 1460 356 g235 -2040 1460 237 g192 5240 1460 297 odummy35 1580 1460 357 g233 -2100 1460 238 g194 5180 1460 298 odummy36 1520 1460 358 g231 -2160 1460 239 g196 5120 1460 299 odummy37 1460 1460 359 g229 -2220 1460 240 g198 5060 1460 300 odummy38 1400 1460 360 g227 -2280 1460
hd66774 rev. 1.0 july 2002 13 no. pin name x (um) y (um) no. pin name x (um) y (um) no. pin name x (um) y (um) 361 g225 -2340 1460 421 g105 -5940 1460 - tg1 -6740 1430 362 g223 -2400 1460 422 g103 -6000 1460 - tg2 6740 1430 363 g221 -2460 1460 423 g101 -6060 1460 364 g219 -2520 1460 424 g99 -6120 1460 365 g217 -2580 1460 425 g97 -6180 1460 366 g215 -2640 1460 426 g95 -6240 1460 367 g213 -2700 1460 427 g93 -6300 1460 368 g211 -2760 1460 428 g91 -6360 1460 369 g209 -2820 1460 429 g89 -6420 1460 370 g207 -2880 1460 430 g87 -6480 1460 371 g205 -2940 1460 431 g85 -6540 1460 372 g203 -3000 1460 432 g83 -6600 1460 373 g201 -3060 1460 433 dummy4 -6870 1470 374 g199 -3120 1460 434 g81 -6860 1300 375 g197 -3180 1460 435 g79 -6860 1240 376 g195 -3240 1460 436 g77 -6860 1180 377 g193 -3300 1460 437 g75 -6860 1120 378 g191 -3360 1460 438 g73 -6860 1060 379 g189 -3420 1460 439 g71 -6860 1000 380 g187 -3480 1460 440 g69 -6860 940 381 g185 -3540 1460 441 g67 -6860 880 382 g183 -3600 1460 442 g65 -6860 820 383 g181 -3660 1460 443 g63 -6860 760 384 g179 -3720 1460 444 g61 -6860 700 385 g177 -3780 1460 445 g59 -6860 640 386 g175 -3840 1460 446 g57 -6860 580 387 g173 -3900 1460 447 g55 -6860 520 388 g171 -3960 1460 448 g53 -6860 460 389 g169 -4020 1460 449 g51 -6860 400 390 g167 -4080 1460 450 g49 -6860 340 391 g165 -4140 1460 451 g47 -6860 280 392 g163 -4200 1460 452 g45 -6860 220 393 g161 -4260 1460 453 g43 -6860 160 394 g159 -4320 1460 454 g41 -6860 100 395 g157 -4380 1460 455 g39 -6860 40 396 g155 -4440 1460 456 g37 -6860 -20 397 g153 -4500 1460 457 g35 -6860 -80 398 g151 -4560 1460 458 g33 -6860 -140 399 g149 -4620 1460 459 g31 -6860 -200 400 g147 -4680 1460 460 g29 -6860 -260 401 g145 -4740 1460 461 g27 -6860 -320 402 g143 -4800 1460 462 g25 -6860 -380 403 g141 -4860 1460 463 g23 -6860 -440 404 g139 -4920 1460 464 g21 -6860 -500 405 g137 -4980 1460 465 g19 -6860 -560 406 g135 -5040 1460 466 g17 -6860 -620 407 g133 -5100 1460 467 g15 -6860 -680 408 g131 -5160 1460 468 g13 -6860 -740 409 g129 -5220 1460 469 g11 -6860 -800 410 g127 -5280 1460 470 g9 -6860 -860 411 g125 -5340 1460 471 g7 -6860 -920 412 g123 -5400 1460 472 g5 -6860 -980 413 g121 -5460 1460 473 g3 -6860 -1040 414 g119 -5520 1460 474 g1 -6860 -1100 415 g117 -5580 1460 475 gtest1 -6860 -1160 416 g115 -5640 1460 417 g113 -5700 1460 418 g111 -5760 1460 419 g109 -5820 1460 420 g107 -5880 1460
hd66774 rev. 1.0 july 2002 14 internal block diagram figure 1 block diagram block functions 1. step-up circuit boosts the vci1 voltage five to nine times. the required voltage is generated by combining double or triple step-up circuit 1 and double, triple, or quadruple step-up circuit 2. the factor is controlled by the register settings. a negative-polarity voltage is also generated according to the boosted voltage. for details on the register settings for the factor, refer to the instructions section. the voltage generated from this circuit is used as the power-supply voltage that is supplied to vgh, vgl, and ddvdh. ddvdh level is supplied to hd66770/772. 2 . liquid-crystal driving-level generation circuit generates the vgoffout, vdh, and vcom levels that are required to drive the tft liquid crystal display, in addition to the voltage generated by the step-up circuit. vdh level is supplied to hd66770/772. 3. interface/register circuit transfers data to the internal control register.
hd66774 rev. 1.0 july 2002 15 4. scan data generation circuit selects the output of the gate line one by one according to the flm signal, cl1 signal, and the setting of the internal control registers. 5. level shifter converts the level of the operating power supply voltage vcc - gnd of the logic circuit to the level of the operating power supply voltage vgh - vgl of the gate-line driving circuit. 6 . gate-line driving circuit selects and outputs either the vgh or the vgoff level according to the selection signal generated at the scan data generation circuit and the level shifter.
hd66774 rev. 1.0 july 2002 16 instructions outline hd66774 has five internal registers. the data is written on to these registers by using a gate serial data interface. this interface can be directly connected to the hd66770 or hd66772 source driver for an automatic transfer of instructions. when an instruction is written on to hd66770/772 via the bus from the cpu, it is output from the serial interface of hd66770/772, and hd66774 receives the instruction to adjust the settings of one of its internal registers. in the bit configuration for the transfer of instructions, the upper three bits are index numbers that indicate the target register of the transfer, and the lower 13 bits are the data. detailed description power control 1 (r00h) figure 2 power control 1 instructions bt2-0: control the step-up factor of the step-up circuit. adjust the step-up factor according to the power-supply voltage to be used. set the output of vlout1 to 5.5 v or lower. dc2-0: set the step-up cycle of the step-up circuit. when the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. adjust the cycle taking into account the display quality and power consumption. ap2-0: adjust the amount of fixed current from the fixed-current source in the internal operational amplifier circuit. when the amount of fixed current becomes large, the driving ability of the operational-amplifier circuit increases. adjust the fixed current taking into account the power-supply ability for each driver and the power consumption. during times when there is no display, such as when the system is in a sleep or a standby mode, ap2-0 can be set to (0, 0, 0) and the power consumption can be reduced by shutting down the operational amplifier. slp: sets the sleep mode. when slp = 1, g1 to g240 and gtest1 to gtest4 are output as gnd, and bits ap2-0 are all fixed to 0. this stops the operation of the power-supply circuit. the state of the slp bit does not change the values of these bits. gon: when gon = 0 and disptmg = 0, g1 to g240 and gtest1 to gtest4 are output as gnd. the vcom output is also fixed to gnd. when gon = 1, g1 to g240 are normally output and gtest1 to gtest4 output vgh/vgoff level according to the state of cad bit.
hd66774 rev. 1.0 july 2002 17 vcomg: when vcomg = 0, the low-level voltage of vcom becomes gnd, and the amplifier for the negative voltage and step-up circuit 4 stop. this enables low-power consumption. when vcomg = 1, a positive or a negative voltage (1.0 v to ? vci + 0.5 v) of vcoml can be output. at this time, use the flow of power-supply setting. when vcomg = 0, if the vcom alternation is driven, the settings of vdv4-0 become invalid. adjust the alternating amplitudes of vcom and vgoff with vcm4-0 in the vcomh settings. table 2 bt bits and vlout1 and vlout2 outputs bt2 bt1 bt0 vlout1 output vlout2 output notes * capacitor connection terminal 0 0 0 2 x vci1 3 x vci2 vlout2 = vci1 x six times vlout1 to vlout4,c11 ?} , c21 ?} ,c22 ?} ,c31 ?} ,c41 ?} 0 0 1 2 x vci1 4 x vci2 vlout2 = vci1 x eight times vlout1 to vlout4,c11 ?} , c21 ?} ,c22 ?} ,c23 ?} ,c31 ?} ,c41 ?} 0 1 0 3 x vci1 3 x vci2 vlout2 = vci1 x nine times vlout1 to vlout4,c11 ?} , c12 ?} ,c21 ?} ,c22 ?} ,c31 ?} ,c41 ?} 0 1 1 3 x vci1 2 x vci2 vlout2 = vci1 x six times vlout1 to vlout4,c11 ?} , c12 ?} ,c21 ?} ,c22 ?} ,c31 ?} ,c41 ?} 1 0 0 2 x vci1 vci1 + 2 x vci2 vlout2 = vci1 x five times vlout1 to vlout4,c11 ?} , c21 ?} ,c22 ?} ,c31 ?} ,c41 ?} 1 0 1 2 x vci1 vci1 + 3 x vci2 vlout2 = vci1 x seven times vlout1 to vlout4,c11 ?} , c21 ?} ,c22 ?} ,c23 ?} ,c31 ?} ,c41 ?} 1 1 0 step-up stopped 3 x vci2 vlout2 = vci2 x three times vlout1 to vlout4,c21 ?} , c22 ?} ,c31 ?} ,c41 ?} 1 1 1 setting inhibited setting inhibited setting inhibited ?\ note: the step-up factors of vlout2 are deri ved from vci1 when vlout1 and vci2 are shorted. the conditions of vlout1 5.5 v and vlout2 16.5 v must be satisfied. table 3 dc bits and step-up cycle dc2 dc1 dc0 step-up cycle in step-up circuit 1 step-up cycle in step-up circuits 2/3/4 0 0 0 dcclk divided by four dcclk divided by 16 0 0 1 dcclk divided by two dcclk divided by 16 0 1 0 dcclk dcclk divided by 16 0 1 1 dcclk divided by two dcclk divided by four 1 0 0 dcclk divided by four dcclk divided by eight 1 0 1 dcclk divided by two dcclk divided by eight 1 1 0 dcclk dcclk divided by eight 1 1 1 dcclk dcclk divided by four
hd66774 rev. 1.0 july 2002 18 table 4 ap bits and amount of current in operational amplifier ap2 ap1 ap0 amount of current in operational amplifier 0 0 0 operation of the operational amplifier and step-up circuit stops. 0 0 1 small 0 1 0 small medium 0 1 1 medium 1 0 0 medium large 1 0 1 large 1 1 0 setting inhibited 1 1 1 setting inhibited voltage setting 1 (r01h) figure 3 voltage setting 1 instructions vc2-0: adjust the vreg1out, vreg2out, and vciout voltages to a fraction of vci. pon: starts operation of step-up circuit 3. the operation stops when pon = 0 and starts when pon = 1. for the timing when pon = 1, refer to the flow of power-supply setting section. vrh3-0: set the amplified factor of the vreg1out voltage (the voltage for the vreg1 reference voltage when the vdh and vcom amplification is generated). these bits amplify the voltage 1.45 to 2.85 times the voltage set by vc2-0. vrl3-0: set the amplified factor of the vreg2out voltage (the voltage for the vreg2 reference voltage when vgoff is generated). these bits amplify the voltage -3 to -9.5 times the voltage set by vc2-0. note that the reference voltage of vreg2out is vci. cad: set this bit according to the structure for the tft-display retention capacitor. cad = 0: set this bit when the cst retention capacitor is structured . the vgoffout outputs the vgoff l level regardless of the vcom alternating drive. cad = 1: set this bit when the cadd retention capacitor is structured. at the vcom alternating drive, the vgoff out voltage is output in the vgoffl voltage reference by the amount of vcom alternating amplitude. gtest1 to gtest4 output vgh/vgoff levels in the timing which is shown in figure 4.
hd66774 rev. 1.0 july 2002 19 table 5 vc settings and internal reference voltage vc2 vc1 vc0 regp and vciout output voltage regn output voltage 0 0 0 0.92 x vci 0.08 x vci 0 0 1 0.83 x vci 0.17 x vci 0 1 0 0.73 x vci 0.27 x vci 0 1 1 0.68 x vci 0.32 x vci 1 0 0 vci *2 gnd 1 0 1 setting inhibited setting inhibited 1 1 0 setting inhibited setting inhibited 1 1 1 setting inhibited setting inhibited note: 1. leave regp and regn pins open because the voltage set above is output for regp and regn. 2. when vc2-0=100, vciout output is hi-z. table 6 vrh bits and vreg1out voltage vrh3 vrh2 vrh1 vrh0 vreg1out voltage 0 0 0 0 regp x 1.45 times 0 0 0 1 regp x 1.55 times 0 0 1 0 regp x 1.65 times 0 0 1 1 regp x 1.75 times 0 1 0 0 regp x 1.80 times 0 1 0 1 regp x 1.85 times 0 1 1 0 regp x 1.90 times 0 1 1 1 stopped 1 0 0 0 regp x 2.175 times 1 0 0 1 regp x 2.325 times 1 0 1 0 regp x 2.475 times 1 0 1 1 regp x 2.625 times 1 1 0 0 regp x 2.700 times 1 1 0 1 regp x 2.775 times 1 1 1 0 regp x 2.850 times 1 1 1 1 stopped note: adjust the settings between the voltage set by vc2-0 and vrh0 to vrh3 so that the vreg1out voltage is lower than 5.0 v.
hd66774 rev. 1.0 july 2002 20 table 7 vrl bits and vreg2out voltage vrl3 vrl2 vrl1 vrl0 vreg2out voltage 0 0 0 0 vci -(vci ? regn) x 3.0 times 0 0 0 1 vci -(vci ? regn) x 3.5 times 0 0 1 0 vci -(vci ? regn) x 4.0 times 0 0 1 1 vci -(vci ? regn) x 4.5 times 0 1 0 0 vci -(vci ? regn) x 5.0 times 0 1 0 1 vci -(vci ? regn) x 5.5 times 0 1 1 0 vci -(vci ? regn) x 6.0 times 0 1 1 1 stopped 1 0 0 0 vci -(vci ? regn) x 6.5 times 1 0 0 1 vci -(vci ? regn) x 7.0 times 1 0 1 0 vci -(vci ? regn) x 7.5 times 1 0 1 1 vci -(vci ? regn) x 8.0 times 1 1 0 0 vci -(vci ? regn) x 8.5 times 1 1 0 1 vci -(vci ? regn) x 9.0 times 1 1 1 0 vci -(vci ? regn) x 9.5 times 1 1 1 1 stopped notes: 1. adjust the settings between the voltage set by vci ? (vc2-0) voltage and vrl0 to vrl3 so that the vreg2out voltage is higher than ? 16.0 v. figure 4 output timing for gtest1 to gtest4 voltage setting 2 (r02h) figure 5 voltage setting 2 instructions vcm4-0: set the vcomh voltage (a high-level voltage at the vcom alternating drive). these bits amplify the vcomh voltage 0.4 to 0.98 times the vreg1 voltage. when vcom4-0 = 1,
hd66774 rev. 1.0 july 2002 21 the adjustment of the internal volume stops, and vcomh can be adjusted from vcomr by an external resistor. vdv4-0: set the alternating amplitudes of vcom and vgoff at the vcom alternating drive. these bits amplify vcom and vgoff 0.6 to 1.23 times the vreg1 voltage. when the vcom alternation is not driven, the settings become invalid. table 8 vcm4-0 bits and vcomh voltage vcm4 vcm3 vcm2 vcm1 vcm0 vcomh voltage 0 0 0 0 0 vreg1 x 0.40 times 0 0 0 0 1 vreg1 x 0.42 times 0 0 0 1 0 vreg1 x 0.44 times : : : : : : 0 1 1 0 0 vreg1 x 0.64 times 0 1 1 0 1 vreg1 x 0.66 times 0 1 1 1 0 vreg1 x 0.68 times 0 1 1 1 1 the internal volume stops, and vcomh can be adjusted from vcomr by an external variable resistor. 1 0 0 0 0 vreg1 x 0.70 times 1 0 0 0 1 vreg1 x 0.72 times 1 0 0 1 0 vreg1 x 0.74 times : : : : : : 1 1 1 0 0 vreg1 x 0.94 times 1 1 1 0 1 vreg1 x 0.96 times 1 1 1 1 0 vreg1 x 0.98 times 1 1 1 1 1 the internal volume stops, and vcomh can be adjusted from vcomr by an external variable resistor. note: adjust the settings between vreg1 and vcm0 to vcm4 so that the vcomh voltage is lower than vdh.
hd66774 rev. 1.0 july 2002 22 table 9 vdv4-0 bits and vcom amplitude vdv4 vdv3 vdv2 vdv1 vdv0 vcom amplitude 0 0 0 0 0 vreg1 x 0.60 times 0 0 0 0 1 vreg1 x 0.63 times 0 0 0 1 0 vreg1 x 0.66 times : : : : : : 0 1 1 0 0 vreg1 x 0.96 times 0 1 1 0 1 vreg1 x 0.99 times 0 1 1 1 0 vreg1 x 1.02 times 0 1 1 1 1 setting inhibited 1 0 0 0 0 vreg1 x 1.05 times 1 0 0 0 1 vreg1 x 1.08 times 1 0 0 1 0 vreg1 x 1.11 times 1 0 0 1 1 vreg1 x 1.14 times 1 0 1 0 0 vreg1 x 1.17 times 1 0 1 0 1 vreg1 x 1.20 times 1 0 1 1 0 vreg1 x 1.23 times 1 0 1 1 1 setting inhibited 1 1 ?? ?? ?? setting inhibited note: adjust the settings between vreg1 and vdv0 to vdv4 so that the vcom and vgoffout amplitudes are lower than 6.0 v. output start-position control and number of valid lines control (r06h) output scan-direction control and output scan-method control (r07h) figure 6 r06h and r07h instructions gs: selects the output scan direction of the gate driver. for description on the gs value and the scan direction, refer to the section of scan mode setting. scn4-0: set the output start position. according to the correspondence between the setting values and the output start position in table 11, start driving the gate line by the gate-line selection circuit. nl4-0: set the number of valid lines from the output start position. according to the correspondence between the setting values and the valid lines in table 12, drive the gate line for the number of valid lines using the gate-line selection circuit.
hd66774 rev. 1.0 july 2002 23 set the nl4-0 and scn4-0 so that (output start position + number of valid lines) - 1 240 lines. table 10 correspondence between scn4-0 and output start position output start position scn4 scn3 scn2 scn1 scn0 scm1 = gnd scm2 = gnd gs = 0 scm1 = gnd scm2 = gnd gs = 1 scm1 = vcc scm2 = gnd gs = 0 scm1 = vcc scm2 = gnd gs = 1 scm1 = vcc scm2 = vcc gs = 0 scm1 = vcc scm2 = vcc gs = 1 0 0 0 0 0 g1 g2 g1 g240 g1 g240 0 0 0 0 1 g17 g18 g17 g224 g9 g232 0 0 0 1 0 g33 g34 g33 g208 g17 g224 0 0 0 1 1 g49 g50 g49 g192 g25 g216 0 0 1 0 0 g65 g66 g65 g176 g33 g208 0 0 1 0 1 g81 g82 g81 g160 g41 g200 0 0 1 1 0 g97 g98 g97 g144 g49 g192 0 1 1 1 1 g113 g114 g113 g128 g57 g184 0 1 0 0 0 g129 g130 g129 g112 g65 g176 0 1 0 0 1 g145 g146 g145 g96 g73 g168 0 1 0 1 0 g161 g162 g161 g80 g81 g160 0 1 0 1 1 g177 g178 g177 g64 g89 g152 0 1 1 0 0 g193 g194 g193 g48 g97 g144 0 1 1 0 1 g209 g210 g209 g32 g105 g136 0 1 1 1 0 g225 g226 g225 g16 g113 g128 0 1 1 1 1 g240 g239 g2 g239 g121 g120 1 0 0 0 0 g224 g223 g18 g223 g129 g112 1 0 0 0 1 g208 g207 g34 g207 g137 g104 1 0 0 1 0 g192 g191 g50 g191 g145 g96 1 0 0 1 1 g176 g175 g66 g175 g153 g88 1 0 1 0 0 g160 g159 g82 g159 g161 g80 1 0 1 0 1 g144 g143 g98 g143 g169 g72 1 0 1 1 0 g128 g127 g114 g127 g177 g64 1 0 1 1 1 g112 g111 g130 g111 g185 g56 1 1 0 0 0 g96 g95 g146 g95 g193 g48 1 1 0 0 1 g80 g79 g162 g79 g201 g40 1 1 0 1 0 g64 g63 g178 g63 g209 g32 1 1 0 1 1 g48 g47 g194 g47 g217 g24 1 1 1 0 0 g32 g31 g210 g31 g225 g16
hd66774 rev. 1.0 july 2002 24 table 11 correspondence between nl4-0 and the number of valid lines nl4 nl3 nl2 nl1 nl0 number of valid lines 0 0 0 0 0 setting inhibited 0 0 0 0 1 16 0 0 0 1 0 24 0 0 0 1 1 32 0 0 1 0 0 40 0 0 1 0 1 48 0 0 1 1 0 56 0 0 1 1 1 64 0 1 0 0 0 72 0 1 0 0 1 80 0 1 0 1 0 88 0 1 0 1 1 96 0 1 1 0 0 104 0 1 1 0 1 112 0 1 1 1 0 120 0 1 1 1 1 128 1 0 0 0 0 136 1 0 0 0 1 144 1 0 0 1 0 152 1 0 0 1 1 160 1 0 1 0 0 168 1 0 1 0 1 176 1 0 1 1 0 184 1 0 1 1 1 192 1 1 0 0 0 200 1 1 0 0 1 208 1 1 0 1 0 216 1 1 0 1 1 224 1 1 1 0 0 232 1 1 1 0 1 240 fld1-0: set the number of valid lines to drive n-line interlacing. table 13 shows the correspondence between the setting value and the number of fields. table 14 shows the scan method. the numbers in circles indicate the scanning order.
hd66774 rev. 1.0 july 2002 25 table 12 correspondence between fld1-0 and n-line interlacing scan fld1 fld0 scan method 0 0 setting inhibited 0 1 one field 1 0 setting inhibited 1 1 three fields
hd66774 rev. 1.0 july 2002 26 table 13 n-line interlacing scan method note: the numbers in circles indicate the scanning order.
hd66774 rev. 1.0 july 2002 27 scan mode setting shift direction of the gate signal can be changed by setting the input levels of the smc1 and 2 pins and the gs bit setting, which enables various types of connections between the liquid crystal display panel and the hd66774.
hd66774 rev. 1.0 july 2002 28 table 14 scan mode setting note: the scm1 and 2 are set by pins and the gs is set by instructions.
hd66774 rev. 1.0 july 2002 29 gate serial transfer the register settings are transferred from hd66770 or hd66772 source driver. the interface consists of a chip select (gcs*), a transfer clock (gcl), and data input (gda) lines. the data transfer starts when the falling edge of the gcs* line indicates that the data is to be transferred. the transfer ends when the rising edge of the gcs* line indicates that the transfer is over. the bits are transferred in 16-bit units, and the data is transferred in the order from msb to lsb. figure 7 format for data transfer
hd66774 rev. 1.0 july 2002 30 reset functions hd66774 sets the internal initialization with the reset pin. input a power-on reset signal when the power is applied as in the case with hd66770 or hd66772. table 15 shows the initial setting values. table 15 initial setting values for registers at reset index code control bit initial value status slp 0 cancels sleep mode. ap2-0 000 stops operational amplifier and step-up circuit operations. dc2-0 000 step-up cycle: equal to dcclk gon 0 vcom and vgoff output control for display off: gnd bt2-0 000 step-up factor vlout2 = vci x five times r00h vcomg 0 vcom output control for display on: gnd vc2-0 000 internal reference voltage of vreg1out/vciout: 0.92 vcc internal reference voltage of vreg2out: 0.08 vcc pon 0 stops operations in the step-up circuit 3. vrh3-0 0000 vreg1out output voltage: regp x 1.45 times vrl3-0 0000 vreg2out output voltage: -(vci - regn) x 3.0 times r01h cad 0 structure for tft-display retention volume: cst vcm4-0 00000 vcomh output voltage: vreg1 x 0.4 times r02h vdv4-0 00000 vcom amplitude: vreg1 x 0.6 times scn4-0 00000 output start position: g1 nl4-0 11101 number of valid lines: 240 r06h gs 0 scan direction control: g1-g240 r07h fld1-0 01 n-line interlacing control: normal scan
hd66774 rev. 1.0 july 2002 31 interface between the liquid crystal display panel figures 8 to 13 show the connection example for the configuration of the 176-dot-row tft-lcd panel using the hd66774, and scn, nl, and gs bit settings and the scanning range of gate lines. figure 8 connection example (1) figure 9 connection example (2)
hd66774 rev. 1.0 july 2002 32 figure 10 connection example (3)
hd66774 rev. 1.0 july 2002 33 figure 11 connection example (4)
hd66774 rev. 1.0 july 2002 34 figure 12 connection example (5)
hd66774 rev. 1.0 july 2002 35 figure 13 connection example (6)
hd66774 rev. 1.0 july 2002 36 flow of power-supply setting apply the power in a sequence as shown in figure 14. the stable times of the oscillation circuit, step-up circuit, and operational amplifier depend on the external resistor or capacitance. after the serial signal transfer has started by te and idx2-0 in hd66770 or hd66772, the mode settings of hd66774 become valid with a delay of cl1 = 1 cyc. take this fact into account when setting the modes.
hd66774 rev. 1.0 july 2002 37 figure 14 flow of power-supply setting (vcc on?j power-on reset and display off issues instructions for power supply setting (1) ?ihd66774) 1ms 10ms or more ( stable time of the hd66770/772 oscillation circuit) 100ms or more (stable times of step-up circuit or operational amplifier) display-on sequence issues instructions for power supply setting (2) ?ihd66774) ?ihd66770/772) bt2-0,dc2-0,ap2-0 vrl3-0,vcm4-0,vdv4-0, vrn4-0/vrp4-0 sap2-0 display on (hd66774) (hd66770/772) issues instructions for other mode setting (hd66774) (hd66770/772) dte=0,d1-0=00 ,gon=0 bits for display off: bits for power-supply initial setting: dte=1, d1-0=11 gon=1 display-off sequence instruction for power supply setting (2) ?ihd66774) ap2-0 for operational amplifier and step-up circuit instruction for power supply setting (1) (hd66770/772) sap2-0 dte=1,d1-0=11 gon=1 gon=0 * 1) note: 1. for the display-on/off seqence,refer to the section on instruction setting flow of hd66770/772 pon=0,vcomg=0, (setting of the source-driver grayscale voltage) issues instructions for power supply setting (4) ?ihd66774) 40 ms or more (stable times of step-up circuits 1 and 2) pon=1 issues instructions for power supply setting (3) ?ihd66774) vcomg=1 power supply bits for power-supply operation-start setting: bits for source-driver operational-amplifier operation-start setting: ap2-0=000,vc2-0,vrh3-0,cad, bit for step-up circuit-4 operation start : bit for step-up circuit-3 operation start : 40 ms or more (stable times of step-up circuits 4) bits for display on: power -on sequence power -off sequence normal display bits for display on: * 1) bits for display off: display-off dte=0,d1-0=00 bits for source-driver operational-amplifier operation-stop setting: bits for power-supply stop setting: (vcc off?j power supply
hd66774 rev. 1.0 july 2002 38 configuration of internal power-supply generation circuit figure 15 shows a configuration of the voltage generation circuit of hd66774. the step-up circuits consist of step-up circuits 1 to 4. step-up circuit 1 doubles or triples the voltage supplied to vci1, and that voltage is doubled, tripled, or quadrupled in step-up circuit 2. step-up circuit 3 reverses the vgh level with reference to gnd and generates the vgl level. step-up circuit 4 reverses the vci level with reference to gnd and generates the vcl level. these step-up circuits generate power supplies required for tft-lcd driving. reference voltages vdh, vcom, and vgoff for the hd66770 or hd66772 grayscale voltage are amplified in amplification circuits 1 and 2 from the internal-voltage adjustment circuit, regp or regn voltage, and generate each level depending on that voltage. the vcom and vgoff voltages can be alternated with any voltages. connect ddvdh and vdh to hd66770 or hd66772, and vcom to the panel and hd66770 or hd66772.
hd66774 rev. 1.0 july 2002 39 figure 15 configuration of the internal power-supply circuit c11+ c12- c12+ c21- c21+ c22- c22+ c23- c23+ c11- vci2 vci1 gnd vgh vcc hd66774 vlout2 vlout1 vciout vci vgl c31- c31+ vlout3 vcomh vdh vreg2 out vreg2 vreg1 out vreg1 vcomr vdh vcom vcoml vgoffh vgoffl regp vci regn vci3 vcl c41- c41+ vlout4 vci4 gnd vci vci ddvdh ddvdh testa1 testa2 testa3 testa4 vgoffout vgoff ?? in the case of vcomg = 1 ?? in the case of cad = 1 amplification circuit2(vgoff adjustment) amplification circuit2(vgoff adjustment) amplification circuit1(vdh adjustment) vcomh adjustment circuit vcom amplitude adjustment circuit vcomh output amplifier vcoml output amplifier vgoff amplitude adjustment circuit vgoffh output amplifier voltage adjust ment circuit vciout output amplifier step-up circuit1 step-up circuit2 step-up circuit3 step-up circuit4 gate driver vgoffl output amplifier ?? in the case of cad = 1 * 1 ?? vciout in the case of use adjuste the vcomh voltage (when using an external variable resistor) note: the capacitor is 0.1uf (b characteristics use the 1uf ( b characteristics)capacitor for other positions connect the capacitor for stabilization to test3 according to the display quality and power consumption.
hd66774 rev. 1.0 july 2002 40 pattern diagrams for voltage setting figure 16 shows a pattern diagram for the hd66774 voltage setting and an example of waveforms when hd66774 is combined with hd66770 or hd66772. figure 16 pattern diagram and an example of waveforms vlout2 (+9?`+16.5v) gnd (0v) vcc (1.7?`3.3v) vci (2.5?`3.6v) vcoml (vcl+0.5?`1.0v) vgoffh (vgl+4.0v?`-5.0v) vgoffl (vgl+0.5v?`-5.0v) vlout3 (-9?`-16.5v) vciout vreg2out vc2-0 vrl3-0 vdv4-0 vlou4(-3.6?`-2.5v) (-1?{) vci1 bt2-0 bt2-0 (-1?{) vlout1 (+4.5?`+5.5v) vdh (3.0v?`ddvdh-0.5v) vcomh (3.0v?`vdh) vreg1out vrh3-0 vcm4-0 ddvdh vcl vgl vgh ?u?????? vgh vcomh vcoml vgoffh vgoffl vdh note?f adjust the conditions of vlout1-vdh>0.5v?avcoml-vlout4>0.5v?a and vgoff-vlout3>0.5v with loads because the differ depending on the display load to be driven. in addtion, vci can be directly input to vci1. s?? (hd66770/772 output) ?f?? (hd66774 output)
hd66774 rev. 1.0 july 2002 41 example of system configuration figure 17 shows a tft-lcd panel with 132 (horizontal)-by-176 (vertical) dots, configured by using the hd66770 source driver. figure 17 system configuration
hd66774 rev. 1.0 july 2002 42 example of connection to hd66770 connection differs according to the voltage setting of vcom. figure 18 shows an example of connection to hd66770 when vcoml < 0 v and 0 v vcoml < 5.5 v. notes: 1. all vcc and gnd input to hd66770 and hd66774 must be the same. 2. leave the eq and vcom pins of hd66770 open. set the eq pin of hd66774 to gnd. 3. use the 1- m f capacitor (b characteristics) as a capacitor for stabilization to be connected. 4. there is no description of how to connect the capacitors of c11- to c12-, c11+ to c12+, c21- to c23-, c21+ to c23+, c31-, c31+, c41-, and c41+ of hd66774. connect these capacitors according to the hd66774 pin functions. 5. apply 2.5 to 3. 6 v to vci by using an external power supply, and connect vciout to vci1 or apply 2.75 v or lower to vci1 by using an external power supply. apply 2.5 to 3.6 v or lower to vci4 by using an external power supply. 6. conncet the shottky barrier diode when vf = 0.4 v/20 ma and vr 3 30 v. 7. use the 0.1- m f capacitor (b characteristics) as a capacitor for stabilization to be connected. 8 . use 200-k w or higher variable resistor. figure 18 example of connection to hd66770 when vcoml < 0 v cl1 flm gcs* gcl gda vdh hd66770 hd66774 vgh vgl vdh m eq vcomr -display vcc,vci ,vci4 gnd vreg1out vreg1 vreg2out vreg2 vcc gnd vcom ?? ?p?j ?? ?p?j ?? ?q) ?? ?q) ?? ?r?j ?? ?r?j ?? ?r?j ?? ?r?j ?? ?r?j ?? ?r?j ddv dh ?? ?r?j ?? ?r?j ?? ?u?j ?? ?r?j o pen v0 v1n v1p v3 p v60n v60p v3n ?? ?v?j ?? ?v?j v61p v62n v62p v61n ?? ?v?j testa1 testa2 testa3 testa4 ?? ?v?j ?? ?r?j dcclk disptmg ?? ?w?j ?? ?r?j o pen vlout3 vci2 vci3 vgoffh vgoffl vgl vlout1 vlout2 vcom vdh dcclk m eq gcl gda ddvdh vgh vcomh vcoml vciout vci1 vlout4 vcl cl1 flm disptmg vgoff * 2) * 5 ) * 5 ) to the tft counter electrode gcs * vgoffout
hd66774 rev. 1.0 july 2002 43 notes: 1. all vcc and gnd input to hd66770 and hd66774 must be the same. 2. leave the eq and vcom pins of hd66770 open. set the eq pin of hd66774 to gnd. 3. use the 1- m f capacitor (b characteristics) as a capacitor for stabilization to be connected. 4. there is no description of how to connect the capacitors of c11- to c12-, c 11+ to c12+, c21- to c23-, c21+ to c23+, c31-, c31+, c41-, and c41+ of hd66774. connect these capacitors according to the hd66774 pin functions. 5. apply 2.5 to 3. 6 v to vci by using an external power supply, and connect vciout to vci1 or apply 2.75 v or lower to vci1 by using an external power supply. apply 2.5 to 3.6 v or lower to vci4 by using an external power supply. 6. conncet the shottky barrier diode when vf = 0.4 v/20 ma and vr 3 30 v. 7. use the 0.1- m f capacitor (b characteristics) as a capacitor for stabilization to be connected. 8 . use 200-k w or higher variable resistor. figure 18 example of connection to hd66770 when vcoml < 0 v cl1 flm gcs* gcl gda vdh hd66770 hd66774 vgh vgl vdh m eq vcomr -display vcc,vci ,vci4 gnd vreg1out vreg1 vreg2out vreg2 vcc gnd vcom ?? ?p?j ?? ?p?j ?? ?q) ?? ?q) ?? ?r?j ?? ?r?j ?? ?r?j ?? ?r?j ?? ?r?j ?? ?r?j ddv dh ?? ?r?j ?? ?r?j ?? ?u?j ?? ?r?j o pen v0 v1n v1p v3 p v60n v60p v3n ?? ?v?j ?? ?v?j v61p v62n v62p v61n ?? ?v?j testa1 testa2 testa3 testa4 ?? ?v?j ?? ?r?j dcclk disptmg ?? ?w?j ?? ?r?j o pen vlout3 vci2 vci3 vgoffh vgoffl vgl vlout1 vlout2 vcom vdh dcclk m eq gcl gda ddvdh vgh vcomh vcoml vciout vci1 vlout4 vcl cl1 flm disptmg vgoff * 2) * 5 ) * 5 ) to the tft counter electrode gcs * vgoffout
hd66774 rev. 1.0 july 2002 44 figure 19 shows an example of connection to hd66770 source driver when 0 vcoml < 5.5 v. notes: 1. all vcc and gnd input to hd66770 and hd66774 must be the same. 2. connect the eq pins of hd66770 and hd66774. the vcom pin must be connected to the vcom pin of hd66774. do not set the vcom voltage higher than 5.5 v. 3. use the 1- m f capacitor (b characteristics) as a capacitor for stabilization to be connected. 4. there is no description of how to connect the capacitors of c11- to c12-, c11+ to c12+, c21- to c23-, c21+ to c23+, c31-, c31+, c41-, and c41+ of hd66774. connect these capacitors according to the hd66774 pin functions. 5. apply 2.5 to 3.6 v to vci by using an external power supply, and connect vciout to vci1 or apply 2.75 v or lower to vci1 by using an external power supply. apply 2.5 to 3.6 v to vci4 by using an external power supply. 6. conncet the shottky barrier diode when vf = 0.4 v/20 ma and vr 3 30 v. 7. use the 0.1- m f capacitor (b characteristics) as a capacitor for stabilization to be connected. 8. use 200-k w or higher variable resistor. figure 19 example of connection to hd66770 when 0 v vcoml < 5.5 v vgl vlout1 vlout2 cl1 flm gcs* gcl gda vdh hd66770 hd66774 vcom vgoffout vgh vlout3 vgl vdh vdh m eq ddvdh vgh vcomr vcomh vcoml vcc,vci ,vci4 gnd vciout vci1 vreg1out vreg1 vreg2out vreg2 vcc gnd vcom * ?p?j ???p?j * ?q) * ?q) * ?r?j * ?r?j * ?r?j * ?r?j * ?r?j ddv dh * ?r?j * 5?j vlout4 vcl * ?r?j vci2 * ?u?j vci3 * ?r?j * ?r?j v0 v1n v1p v3 p v60n v60p v3n * ?v?j * ?v?j v61p v62n v62p v61n * ?v?j testa1 testa2 testa3 testa4 * ?v?j * ?r?j dcclk m eq gcs* gcl gda vgoffh vgoffl * 2 ) * ?r?j disptmg cl1 flm dcclk disptmg vgoff * ?w?j * 5?j to the tft -display counter electrode
hd66774 rev. 1.0 july 2002 45 specifications for the capacitor connected to hd66774 table 16 shows the specifications for the capacitor connected to hd66774. table 16 specifications for the capacitor connected to hd66774 product capacitor recommended breakdown voltage connected pin (19 in total) 6 v vreg1out, vciout *4 , c41-/+, vlout4, vcomh, vcoml *3 10 v vlout1, c11-/+, c12-/+, c21-/+, c22-/+, c23-/+ 1 m f (b characteristics) 25 v vreg2out, vlout2, vlout3, c31-/+, vgoffh *2 , vgoffl testa3 *2 hd66774 0.1 m f (b characteristics) 25 v notes: 1. the step-up circuit capacitor c is required at different part according to the setting of step-up circuit magnification. r efer to the instruction bt2 -0. 2. required when instruction cad=1 (cadd mode). 3. required when instruction vcomg=1 . 4. required when instruction vc2-0= ? 0 ** ? (vciout used for output).
hd66774 rev. 1.0 july 2002 46 absolute maximum ratings item symbol ratings unit notes logic circuit vcc -0.3 to +7.0 v 1 vci - gnd -0.3 to +7.0 v 1 ddvdh - gnd -0.3 to +7.0 v 1 gnd - vcl -0.3 to +4.6 v 1 ddvdh - vcl -0.3 to +10.0 v vgh - gnd -0.3 to +18.5 v 1 power supply voltage lcd drive circuit gnd - vgl -0.3 to +18.5 v 1 input voltage vt1 -0.3 to vcc + 0.3 v 1, 2 operating temperature topr -40 to +85 c storage temperature tstg -55 to +110 c notes: 1. voltage from gnd. 2. applies to the eq, dcclk, gcs*, gda, gcl, m, disptmg, cl1, flm, reset*, scm1, scm2, opoff, dctest, and pontest pins. note: if the lsi is used beyond the ab ove maximum ratings, it may be permanently damaged. it should always be used within its specified operating range for normal operation to prevent malfunction or degraded reliability.
hd66774 rev. 1.0 july 2002 47 electrical characteristics dc characteristics (vcc = 1.7 to 3.6 v, gnd = 0 v, vgh - vgl = 18 to 33 v, ta = -40 to +85 o c) *1 item symbol test condition min. typ. max. unit notes input high voltage vih 0.7 x vcc - vcc v 2 input low voltage vil 0 - 0.3 x vcc v 2 driver on resistance ronh vgh ? vgl = 33 v, iload = 100 m a - - 10 k w 3 driver on resistance ronl vgh ? vgl = 33 v, iload = 100 m a - - 10 k w 3 input leakage current iil vin = 0 to vcc -2.5 - 2.5 m a 2 operating frequency fopr 10 - 100 khz 4 current consumption 1 icc vcc - gnd = 3 v, fm = 12.3 khz, fcl1 = 24.6 khz 20 m a 5 current consumption 2 ici vcc - gnd = 3 v, vci - gnd = 3 v, fm = 12.3 khz, fcl1 = 24.6 khz, fdcclk = 24.6 khz, vgh - vgl = 33 v 850 m a 5 notes: 1. for electrical characteristics, guaranteed at 85 c. 2. applies to the eq, dcclk, gcs*, gda, gcl, m, disptmg, cl1, flm, reset*, scm1, scm2, opoff, dctest, and pontest pins. 3. resistance values between the g and v pins (vgh or vgoff) when the load current flows one of g1 to g240 pins. the following condition is specified. g1 to g240 pins that are not measured are left open. vgh = +16.5 v, vgoff = -16.5 v, iload = 100 m a 4. applies to the cl1 pin. 5. values when no load current flows on the vdh, vgh, vgl, vgoff, and vcom pins, and when instruction settings are vc2-0 = 000 (vci x 0.92), ap2-0 = 011 (amount of operational amplifier current), bt2-0 = 000 (step-up circuit 1: double, step-up circuit 2: triple), dc2-0 = 100 (step-up synchronization with step-up circuit 1: dcclk, step-up synchronization with step-up circuits 2, 3, and 4: 8-divided dcclk), vcomg = 1, and cad = 1.
hd66774 rev. 1.0 july 2002 48 ac characteristics (vcc = 1.8 to 3.3 v, vgh - vgl = 18 to 33 v) item symbol pin min. typ. max. unit notes cl1 high-level width tcwh cl1 1.0 - - m s cl1 low-level width tcwl cl1 1.0 - - m s cl1 cycle time tcyc cl1 10 - - m s cl1/gcl rising time tr cl1 - - 100 ns cl1/gcl falling time tf cl1 - - 100 ns flm setup time tfs flm, cl1 1.0 - - m s flm hold time tfh flm, cl1 1.0 - - m s gcl cycle time tcycg gcl 2.5 - - m s gcl high-level width tcwhg gcl 1.0 - - m s gcl low-level width tcwlg gcl 1.0 - - m s gda setup time tgds gcl, gda 1.0 - - m s gda hold time tgdh gcl, gda 1.0 - - m s gcs low setup time tgsl gcl, gcs* 1.0 - - m s gcs high hold time tghh gcl, gcs* 1.0 - - m s output delay time tdd cl1, g - - 1.0 m s
hd66774 rev. 1.0 july 2002 49 (ann.1) the connection of operating voltage & energy consumption will be written down below. condition of measurement?f vgh=16.5v,vgl=-16.5v vgoff=-16.5v,fm=100hz fdcclk=25.6khz,cadd, gon=1,ta=25?? condition of measurement?f vgh=16.5v,vgl=-16.5v vgoff=-16.5v,fm=100hz fdcclk=25.6khz,cadd, booster scale(?~2,?~6) booster (1devide,8devide) op-amp dc current(mid), gon=1,ta=25?? condition of measurement ; dcdc1?~double ?c dcclk?f1devide,vci1=2.75(v)?cta=25?? voltage b ooster circuit ?p (ann.2) the connection of voltage booster & load current will be written down below. vcc vci1 c11+ c11- c12+ c12- c21+ c21- c22+ c22- c23+ c23- c31+ c32- c41+ c42- vlout1 1? f circuit of measurement - + 1?f 0 200 400 600 800 1000 1200 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4.0 vci [v] ici[ua] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.5 2.0 2.5 3.0 3.5 4.0 vcc [v] cc[ua] i 5.2 5.3 5.4 5.5 5.6 5.7 5.8 typ 5.0 5.1 -1200 -1000 -800 -600 -400 -200 0 il [ua] electrical characteristics notes
hd66774 rev. 1.0 july 2002 50 condition of measurement; dcdc2?~3times, dcclk?f8devide,vci2=5.5(v)?cta=25?? voltage booster circuit 2 circuit of measurement vcc vci2 c11+ c11- c12+ c12- c21+ c21- c22+ c22- c23+ c23- c31+ c32- c41+ c42- vlout2 1? f - + 1?f - + 1?f condition of measurement?g dcdc3?~-1time, dcclk?f8devide?cvci3=16.5(v)?cta=25?? voltage booster circuit 3 condition of measurement ?g dcdc4?~-1time?c dcclk?f8?cvci4=2.5(v)?cta=25?? vcc vci3 c11+ c11- c12+ c12- c21+ c21- c22+ c22- c23+ c23- c31+ c32- c41+ c42- vlout3 - + 1?f 1?f vcc vci4 c11+ c11- c12+ c12- c21+ c21- c22+ c22- c23+ c23- c31+ c32- c41+ c42- vlout4 - + 1?f 1?f circuit of mesurement voltage booster circuit 4 circuit of measurement 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 -1000 -800 -600 -400 -200 0 il[ua] typ. -16.5 -16.0 -15.5 -15.0 -14.5 0 100 200 300 400 500 600 il[ua] typ. -2.1 -2.0 typ. -2.3 -2.2 -2.5 -2.4 0 1 00 6 00 200 3 00 4 00 5 00 il [ua]
hd66774 rev. 1.0 july 2002 51 (ann. 3) the connection of vcom & load current will be written down below. vcomh(desired value = 2.5v) vcoml(desired va lue = -2.8v) condition of measurement ?g ddvdh=5.5v?c vcomr=2.5v?cta=25?? condition of measurement ?gddvdh=5.5v vcl=-3.3v?cta=25?? (ann.4) the connectoin of vgoff & load current will be written down below. vgoffh(desired value = -12.0v) vgoffl(desired value = -16.0v) condition of measurement;vgl=-16.5v,ta=25?? condition of measurement ?g vreg2=-16.0v, vgl=-16.5v,ta=25?? 2.0 2.1 2.2 2.3 2.4 2.5 -800 -600 -400 -200 0 il [ua] typ -3.0 -2.9 -2.8 -2.7 -2.6 -2.5 0 200 400 600 800 il [ua] typ -12.1 -12.0 -11.9 -11.8 typ -12.2 -800 -600 -400 -200 0 -16.1 -16.0 -15.9 -15.8 typ -16.2 0 200 400 600 800
hd66774 rev. 1.0 july 2002 52 figure 20 ac timing t f t cwl t cwh 0.7vcc 0.3vcc cl1 0.7vcc t fh t fs flm t cyc t r tdd * 2 setvalue x50 % write note : tdd is specified as the follwing output load capacitor. 30pf 30pf 30pf 30pf 200?? 200?? 200?? 200?? ?f output vgh vgoff 0.7vcc 0.3vcc gcl gda 0.3vcc 0.7vcc 0.3vcc 0.7vcc tgds tgdh gcs * tcycg 0.3vcc tg sl 0.7vcc 0.3vcc tghh t r t f 0.7vcc 0.3vcc t cwhg t cwlg
hd66774 rev. 1.0 july 2002 53 modification history revision 1.0 (jun. 27 .2002) - first release

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